Bipolar integrated logic circuits operate at relatively low voltage logic levels. For example, a LOW or ZERO logic level for transistor-transistor logic (TTL) circuits may be in the 0-0.8 volt range while a HIGH or ONE level may be in the 2.0 volt-to-power supply voltage. Thus, the transition point of a TTL logic circuit is preferably about 1.4 volts.
For large scale integrated field effect transistor circuitry, low threshold complementary metal-oxide semiconductors (CMOS) are used which may operate with supply voltages in the 5 volt range. It is often required to interface TTL circuits with CMOS integrated circuits, thereby necessitating a buffer or level changer to translate from the TTL levels to the CMOS levels.
In designing a simple inverter for use as an input buffer for operating CMOS logic from TTL logic levels, the N-channel current and the P-channel current at the switching point can be expressed as ##EQU1## where K'.sub.N and k'.sub.P are device gain constants,
W.sub.N is the width of an N-channel device, PA1 W.sub.P is the width of a P-channel device, PA1 L.sub.N is the length of an N-channel device, PA1 L.sub.P is the length of a P-channel device, PA1 .DELTA. represents the change in widths or lengths due to the process, PA1 V.sub.gs is the voltage across the gate and source, PA1 V.sub.cc is the power supply voltage, and PA1 V.sub.TN and V.sub.TP are the threshold voltages for the devices.
The switching point for the inverter can be expressed as ##EQU2## where V.sub.INV is the input voltage that yie1ds V.sub.IN =V.sub.out.
An important parameter in digital switching circuits is the delay time required for switching and, therefore, the point at which a logic gate switches must be stable.
Referring now to equations (1) and (2) for I.sub.N and I.sub.P, the parameters which can vary in the production of integrated logic circuits are K'.sub.N, K'.sub.P, .DELTA.W.sub.N, W.sub.P, .DELTA.L.sub.N,.DELTA.L.sub.P, V.sub.TN and V.sub.TP.
Such process variations from chip to chip will result in differing transconductances among the devices. For example, it is possible for K'.sub.P to have a higher value than normal, and K'.sub.N to have a lower value than normal resulting in a high I.sub.P and a low I.sub.N, thereby causing the switch point voltage to be higher than nominal, and the voltage margin between V.sub.INV and the minimum logic ONE input of 2 volts to be decreased. Further, if V.sub.INV is greater than 2 volts, the device would fail to operate. Additionally, a reduction of the voltage margin will increase the delay time of switching since the transconductance of an N device decreases as V.sub.INV increases. V.sub.INV is directly proportional to V.sub.cc and therefore increasing V.sub.cc will reduce the N device transconductance relative to the P device.
Therefore, to ensure a reliable design of an interface between TTL and CMOS logic circuits, compensation is required for supply voltage, process and temperature variations.
A number of interface devices between TTL and CMOS logic circuits is known in the prior art. U.S. Pat. No. 4,380,710 to Cohen et al disclose an interface circuit requiring a quite large chip area and having high parasitic capacitance on the output node. A level shift circuit is described by Hsieh et al in U.S. Pat. No. 4,295,065. This circuit lacks voltage and process compensation. A buffer for NMOS technology is taught by Lin et al in U.S. Pat. Nos. 4,437,025, 4,475,050 to Noufer and 4,471,242 to Noufer et al disclose TTL to CMOS input buffers. Neither provide process compensation and both require relatively high static current.
Other related patents include: U.S. Pat. Nos. 3,676,700, Buchanan; Lattin, 3,708,689; Koo, 4,048,518; and Luke et al, 4,469,959.
There remains a need for a TTL/CMOS interface circuit having voltage, temperature and process compensation as well as low static current drain, fast transition time, and low output parasitic capacitance without requiring excessive chip area.